This invention relates generally to digital signal processing and more particularly to a method and system for reducing power in a parallel-architecture multiplier.
In the art of digital signal processing, power efficiency and speed are becoming increasingly important. As digital signal processing (DSP) chips are designed to operate with higher clock frequencies, one of the critical paths is through the multiplier.
Typically, DSP applications utilize multipliers with an array architecture because of their compact layout and relatively small parasitic wiring capacitance on internal nodes, in addition to the fact that they are generally easier to pipeline than multipliers with a parallel architecture. However, array-architecture multipliers are also slower than equivalent parallel-architecture multipliers.
Simply using a faster multiplier, however, is an unsatisfactory solution to the problem. This is because dynamic power requirements increase linearly with clock frequency. Thus, the higher the clock frequency, the more power that is required for the multiplier.
In accordance with the present invention, a method and system for reducing power in a parallel-architecture multiplier are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, a multiplier is disclosed that provides the speed of a parallel-architecture multiplier and that reduces power requirements by allowing the temporary deactivation of parts of the multiplier when those parts are unnecessary for performing a multiplication.
In one embodiment of the present invention, a multiplier is provided that includes an encoder, a hierarchy of compressors, a bit detector and a switch. The encoder is operable to receive a first and second encoder input. The compressors are coupled to the encoder. The compressors are operable to receive a first number of inputs and to generate a second number of outputs, with the second number being less than the first number. The bit detector is operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range. The bit detector is also operable to deactivate a subset of the compressors when the bit detector determines that the first encoder input is in the reduced precision range. The switch is coupled to a specified one of the compressors. The switch is operable to redirect the path of one of the outputs for the specified compressor such that the subset of the compressors is removed from the path when the bit detector determines that the first encoder input is in the reduced precision range.
Technical advantages of the present invention include providing an improved parallel-architecture multiplier. In particular, a bit detector monitors an input to the multiplier to determine when parts of the multiplier are not needed for multiplying that input. As a result, the unnecessary parts of the multiplier may be temporarily deactivated. Accordingly, the speed of a parallel-architecture multiplier is provided, while power requirements are reduced. In addition, low power, high performance digital signal processing chips may be fabricated with the improved multiplier.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.